Apple’s persistent quest for better performance, longer battery life, and slimmer form factors appears to be driving its research into advanced chip packaging technologies. So-called “2.5D” and “3D” packaging methods stand to offer significant gains in all of these areas by increasing memory bandwidth, reducing power consumption, and freeing up space for higher-capacity batteries.
Apple has been an aggressive adopter of new device packaging methods, mostly thanks to integrated fan-out (InFO) innovations provided by foundry partner TSMC. TSMC’s success has spurred it into further developing and diversifying its packaging offerings, and TSMC has emerged as an industry leader in packaging techniques.
While versions of TSMC’s InFO packaging have brought performance improvements to Apple devices, such as better thermal management and improved package height, it has largely not been a direct enabler of improved electrical performance. This is set to change with future packaging techniques and is already seen in some products that utilize interposers for higher density interconnects to on-package memory, such as High Bandwidth Memory (HBM).
The primary memory candidate for inclusion in such a package would be conforming to the Wide I/O set of standards described by JEDEC, and mentioned by name in several of the patents. This memory improves on LPDDR4 by increasing the number of channels and reducing the transfer speed per channel, thus increasing the overall bandwidth but lowering the energy required per bit.
Interposers do, however, pose several issues for mobile devices. Significantly, they introduce another vertical element to the package, increasing total height. Interposers must also be fabricated on silicon wafers just like active ICs, with their dimensions driven by the footprint of all devices that need to be included in the package. These solutions are typically termed as “2.5D” due to some components being placed laterally with respect to one another rather a true stacking of chips.
Rather than adopt interposers for its products as a next step in advanced packaging, the direction of Apple’s focus, according to several patent applications , appears to be on true “3D” techniques, with logic die such as memory being placed directly on top of an active SoC. Additionally, a patent application from TSMC seems to suggest a level of coordination between Apple and TSMC in these efforts.
3D stacking process flow
The process has similarities to the existing InFO techniques in that they both involve a redistribution layer (RDL) where contacts on a logic die are routed inside a molding compound with the help of vias directly in the molding compound. Where the 3D process diverts from this is that there is now RDL content on both sides of the die, necessitating the use of through-silicon vias (TSV) directly in the logic die so that interconnections can be made with the top of the die. A key feature of these RDL layers is that interconnect pitches finer than available substrate or interposer types is possible.
Subsequent dies could then be attached to the molding compound, mating with the vias and RDL placed in the previous step. This step could be done multiple times, provided each stacked component has TSVs for the next level of integration, and this is already seen in HBM, which allows for the stacking of up to eight DRAM dies.
Side view of memory die (110) attached to SoC (150) in 3D package
Still, this approach has many technical challenges that have prevented its commercialization. TSVs are expensive to implement and are a serious yield detractor to ICs. Electrical isolation from nearby components’ radiated energy can also be a concern, particularly when integrating RF and analog components in a package with other components that would have been separated by space and EMI shielding before. Apple describes techniques to incorporate shielding directly in the package to mitigate this.
Package with integrated EMI shield
This approach also presents thermal challenges since active dies become so closely coupled in mediums that have poor thermal conductivity and shared thermal paths. These concerns extend not only to normal device usage, but also the package integration and any solder reflow steps. Thermal stresses can induce warpage of the packaging components due to differing coefficients of thermal expansion (CTE) amongst the materials utilized in the package. This warpage can lead to broken or separated contacts, resulting in device failure.
The use of a carrier substrate in the process flow mitigates some of the thermal concerns. The direct integration of heatsinks into device packaging is also addressed at various levels of the package assembly, such that higher dissipating die, such as a SoC featuring CPU and GPU cores, could be placed on the bottom of the stack or at a higher level of integration, providing stackup flexibility not seen in previous PoP arrangements.
Package with integrated heatsink component (310)
Embodiments may be applied in applications such as, and not limited to, low power and/or high I/O width memory architecture. Embodiments can enable a short double data rate (DDR) channel to neighboring function units (e.g. SOC, chipsets, etc.) by using RDL and direct chip attach. Embodiments may be particularly applicable for mobile applications that require low power DDR at target performance including high speed and I/O width.
The benefits of the methods described are many. The use of higher bandwidth memory will yield performance improvements. The flexibility of component placement shortens the distance between connected active and passive devices, either lowering the energy required to communicate between them, or reducing parasitic effects that can cause unwanted power loss or dynamic performance degradation. The most notable tasks that stand to benefit are gaming and image processing tasks, which often require large amounts of bandwidth over short time intervals.
Apple Watch Implications
These enhancements would be applicable to all of Apple’s mobile devices, but multiple patent applications specifically mention methods of multiple components married together in a System in Package (SiP), as seen in the current Apple Watch. The methods described below are an enhancement on the existing SiP solutions found in Apple Watch in that they introduce true 3D stacking elements enabled by both TSV and Through Oxide Vias (TOV).
Array of TOVs for connecting stacked die to package pins
In one aspect, embodiments describe system on chip (SoC) die portioning and/or die splitting within an SiP structure (e.g. 3D memory package) in which IP cores such as CPU, GPU, IO, DRAM, SRAM, cache, ESD, power management, and integrated passives may be freely segregated throughout the package, while also mitigating total z-height of the package.
Additionally, the patent describes TSV and TOV pitch in explicit detail, suggesting that keeping package heights down allows them to create very small width vias, with the TOV forming interconnect rows at sizes smaller than even the TSVs. The effect of TSVs stressing active parts of the die, including hurting transistor performance, is also discussed, and the reduced pitches help to mitigate this.
Active die keepout zones around TSVs
Inclusion of RF transceivers and active devices on substrate types not currently used in Apple mobile devices are covered, indicating all types of active and passive components found in Apple Watch products could be housed in the SiP proposed.
Bottom level view of an SiP with stacked heterogenous die interconnected with TSV and TOV
Packages featuring 2.5D and 3D connected components have been in consumer devices for several years, but most of the methods described above have yet to debut in mobile devices. The steps described are set to increase manufacturing complexity, and cost and throughput will likely suffer as a result.
Due to cost and yield concerns, a primary candidate for first inclusion of these methods would be a high-margin, low-quantity device. While the iPhone is the highest margin of Apple’s mobile products, it is also the largest volume category, with a huge initial demand for each generation. The iPad Pro is a good candidate because of its low volume nature and its classification as a high-performance device. The inclusion of 120Hz refresh rate is something that will benefit from increased memory bandwidth, specifically.
The focus of many of these patents seems to be specifically on SiP methods seen in Apple Watch internals. The Apple Watch is a lower-volume device, and it stands to benefit because its internals are extremely sensitive to package size given the importance of its form factor and battery size. It seems reasonable to expect some of the methods described to be incorporated as soon as the next revision of the Apple Watch, and more progressively in future revisions
Amazon Now Taking Pre-Orders For Microsoft’s Surface Go Tablet
A couple of weeks ago Microsoft launched their latest Surface tablet in the form of the Surface Go. Shortly after the launch Microsoft started taking pre-orders for the device via the official Microsoft Store, but in case you prefer doing your shopping on Amazon for whatever reason, Amazon has also started to accept pre-orders for the tablet as well.
In terms of pricing, there is no difference from the Amazon listing and the Microsoft listing. This means that the model with 4GB of RAM and 64GB of storage will retail for $399, while the 8GB RAM and 128GB memory option will retail for slightly more expensive at $549. Some might wonder why shop through Amazon when you can buy it from Microsoft directly, but there are some advantages depending on where you live.
For example some reports have pointed out that over in Spain, Amazon Spain is giving a 25% discount on the higher-end model where instead of it being priced at 599 EUR, it is now priced at 449 EUR, so for our readers in Spain, you will be able to take advantage of this discount. However the downside is that the tablet will only begin shipping to you on the 28th of August for those living in Europe, versus the US where it is set for a release on the 2nd of August which is this coming Thursday.
Mowgli Movie Will Now Release On Netflix In 2019
Mowgli is a live-action Jungle Book adaptation that director Andy Serkis has been working on. Netflix has now purchased the rights to this movie and it will, therefore, be released on the online streaming network. The release date has been moved to 2019 as a result of this development which will now see this movie being released on Netflix first. This movie is different from Disney’s live-action adaptation of the Rudyard Kipling classic which the studio released in 2016.
Rohan Chand stars in the lead role with Christian Bale playing Bagheera, Cate Blanchett playing Kaa, and Benedict Cumberbatch taking on the role of Shere Khan. Andy Serkis himself will be playing Baloo.
This movie was actually supported to be released in 2016 as well but it has been delayed multiple times since then. The first trailer was released recently which mentioned October 19th, 2018 as the theatrical release date.
That was before Netflix had decided to acquire the rights to Mowgli. EW reports that with this acquisition, the release has been delayed yet again. Netflix is going to premiere Mowgli on its platform at some point next year.
Serkis has said that the decision to move the film to Netflix will help avoid a direct comparison with the Disney movie. The platform will also enable the director to have more creative freedom and explore darker themes, going so far as to explore the violence between animals.
New iPad Pro Lineup Might Ditch The Headphone Jack
Ever since Apple ditched the standard 3.5mm headphone jack on recent iPhone models there has been speculation that the company will do this for its other mobile devices as well. A new report has surfaced which claims that the upcoming iPad Pro lineup is not only going to be slightly smaller than its predecessor but will also ditch the 3.5mm headphone jack.
The iPad Pro lineup due next year will reportedly see its dimensions being reduced a little for both the 10.5 inch and 12.9 inch models. The report also reiterates earlier rumors that the new iPad lineup is going to feature FaceID. A recent iOS 12 beta also revealed that there’s a big possibility that this biometric access control system might arrive with the next generation of Apple’s tablet.
The new iPad Pro models might be designed for vertical use as FaceID will reportedly not work when the tablet is in landscape mode. It may also adjust the positions of the Lightning connector and the smart connector for the keyboard for this purpose.
It is as yet unclear when Apple is going to unveil these new tablets. There have been a lot of reports and rumors about them in recent months and they will likely continue in the days to come.
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